重要寄存器

下面寄存器都是位於pcie memory space, bar[0/1] 空間。

Offset 24h: AQA – Admin Queue Attributes

The Admin Submission Queue’s priority is determined by the arbitration mechanism selected, refer to section 4.11. The Admin Submission Queue and Admin Completion Queue are required to be in physically contiguous memory.

Offset 28h: ASQ – Admin Submission Queue Base Address

This register defines the base memory address of the Admin Submission Queue.

Offset 30h: ACQ – Admin Completion Queue Base Address

This register defines the base memory address of the Admin Completion Queue.

上面queue中的每個entry指向的地址落在controller memroy buffer. 就是下面下面兩個寄存器相關的區域。

Offset 38h: CMBLOC – Controller Memory Buffer Location

This optional register defines the location of the Controller Memory Buffer (refer to section 4.7). If CMBSZ is 0, this register is reserved.

Offset 3Ch: CMBSZ – Controller Memory Buffer Size

This optional register defines the size of the Controller Memory Buffer (refer to section 4.7). If the controller does not support the Controller Memory Buffer feature then this register shall be cleared to 0h.

重要數據結構

nvme 重要的數據結構包括submit/completion queue 、scatter/gather list、completion queue entry、controller memroy buffer、name space list、controller list; 命令仲裁機制；

nvme queue

隊列特點

總體來說有兩個特點：
submit / complete queue 是生產區消費者模型；
queue 以循環隊列的數據結構關聯；

隊列長度

受誰決定：indicated in a 16-bit 0’s based field that indicates the number of slots in the queue
最小長度：2 slots;
IO submit/completion queue最大長度：64K slots;
Admin submit/completion queue最多長度：4K slots;

隊列優先級

If the weighted round robin with urgent priority class arbitration mechanism is supported, then host software may assign a queue priority service class of Urgent, High, Medium or Low. If the weighted round robin with urgent priority class arbitration mechanism is not supported, then the priority setting is not used and is ignored by the controller.

隊列標識符

創建的時候，需要指定一個16 bit 的標識符；

深入理解SPDK之四：nvme 協議重點解讀